1. Field of the Invention
The present invention relates to a semiconductor device and an improvement of a breakdown voltage structure in a terminating portion of, for example, a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor) or the like.
2. Related Background Art
A vertical MOSFET structure has been employed in power devices such as a power MOSFET and an IGBT. Particularly, the power MOSFET is a key device essential for increasing efficiency of a switching power supply that is widely used in data communication devices, portable devices, electronic devices, etc. In order to increase the efficiency of the switching power supply, it is important to reduce loss in switching devices, and more particularly, the reduction in ON-resistance has been one of the most important issues in a high breakdown voltage MOSFET used on a primary side of the power supply. As a structure capable of drastically reducing the ON-resistance of the high breakdown voltage MOSFET, a so-called multi RESURF structure, where a drift layer of the MOSFET is replaced with RESURF, has already been proposed and commercialized in part. One example of the multi RESURF structure is shown in a cross-sectional view of FIG. 9. It is to be noted that the same elements in the attached drawings are indicated with the same reference numerals, and repetitive explanations thereof will be appropriately omitted.
Achievement of both the high breakdown voltage and low ON-resistance is attempted using the multi RESURF structure of the MOSFET shown in FIG. 9 in that the MOSFET maintains high breakdown voltage by virtue of depletion due to its charge compensation effect in an OFF-state, and in that currents flow through a high concentration region of the MOSFET in an ON-state. However, present technologies have difficulty in forming such a multi RESURF structure by a method other than a so-called multi epitaxial growth technique in which RESURF N layers and P layers are alternatively laminated. Explaining the multi epitaxial growth technique using the MOSFET shown in FIG. 9, the technique is a method in which there is repeated several times a step where a thin N-type impurity diffusion layer 12 is epitaxially grown on an N++ type semiconductor substrate W, and then a P type impurity diffusion layer 118 and an N type impurity diffusion layer 116 having the same thickness as the P type impurity diffusion layer 118 are formed through desired patterning. This method considerably increases a production cost due to the repetition of the epitaxial growth step, which eliminates the merits that the ON-resistance of the device can be lowered. To overcome this problem of the cost, a so-called trench multi RESURF structure has been proposed in which after a trench is formed, a RESURF N (or P) layer is formed on side faces of the trench (for example, Japanese Patent No. 3291957 (Fujishima) and U.S. Pat. No. 6,040,600 (Minato)). As shown in a cross-sectional view in the upper part of FIG. 10, in the trench multi RESURF structure disclosed by Fujishima an N type impurity diffusion layer (hereinafter referred to simply as the N layer) and a P type impurity diffusion layer (hereinafter referred to simply as the P layer) for charge compensation are repetitively formed and two pairs of N layer/P layer are disposed between two insulating layers 54 buried in trenches TR4. This trench multi RESURF structure is obtained by, for example, forming the trench TR4 in a P type epitaxial growth layer and further forming N layers 56 on two side faces of the trench TR4. In this case, profiles of the N layer 56 may cause variations in charge compensation. As shown by a graph in the lower part of FIG. 10, profile overlapping portions PFPN of the N layer 56 and a P type epitaxial growth layer 58 are automatically charge-compensated, however, if charge amount is not equal between individually remaining portions PFP and PFN, the breakdown voltage of the device is consequently lowered. Since quantity imbalance between an N type impurity and a P type impurity may result in lowered breakdown voltage, such variations would be a disadvantage.
Furthermore, in the example disclosed by Fujishima, the higher an impurity concentration of the P type epitaxial growth layer to become the base is, the higher an impurity concentration of the N layer 56 must be raised for attenuation. Therefore, if the variations are caused in a constant proportion, the absolute values thereof would necessarily become large.
On the other hand, in an example disclosed by Minato as shown in FIG. 11, there is only one pair of N/P layers for charge compensation between two insulating layers 14 buried in repetitive trenches TR2. This trench multi RESURF structure is obtained by forming the trench TR2 and thereafter forming an N layer 16 on one side thereof and a P layer 18 on the other side thereof, as shown by arrows in FIG. 11. The structure disclosed by Minato has no profile overlapping portions between the N/P layers unlike the example of Fijishima, which thus eliminates the necessity of raising the concentrations of the N layer and P layer more than necessary. Therefore, the structure disclosed by Minato has an advantage over characteristic variability. For this reason, it seems as if the structure disclosed by Minato had already solved the disadvantage of the characteristic variability together with the initial problem of the cost.
The structure disclosed by Minato in which the N layer 16 is formed on one side of the trench TR2 and the P layer 18 is formed on the other side thereof can indeed achieve charge compensation between the insulating layers 14 buried in the trenches TR2 in a cell portion of a device, however, only either one of the N layer and P layer exists on an outer side of the insulating layer 14 in a terminating portion surrounding the cell portion of the device. Thus, there is no counterpart impurity diffusion layer for charge compensation in the terminating portion, which causes so-called charge unbalance, thus disadvantageously lowering the breakdown voltage of the device. More details in this regard will be described referring to FIG. 12.
FIG. 12 is a schematic cross-sectional view showing a structure in the terminating portion of the MOSFET in FIG. 11. In an example of the terminating portion shown in the right half part of the FIG. 12, a voltage is applied between a RESURF N layer 88ER connected to a drain electrode 34 via the N++ type semiconductor substrate W and RESURF P layers 52 and 18 connected to a source electrode 32, so that an electric field concentrates at an insulator 14 (region indicated by a broken line C2) in the trench TR2 therebetween. In an example of an opposite side of the terminating portion shown in the left half part of the FIG. 12, an N layer 16 and a P layer 88EL for charge compensation are separated by the insulator 14 in the trench TR2 and thus the P layer 88EL is redundant. In this case, charges (hole) in the P layer 88EL are not discharged even when the voltage is applied, therefore the electric field intensity in this region (indicated by a broken line C4) becomes higher than that in the RESURF part, resulting in failure to obtain the original breakdown voltage of RESURF in the structure shown in FIG. 12. Accordingly, there exists a problem that the structure shown in FIG. 12 cannot offer the desired breakdown voltage.
For a terminating portion of a conventional MOSFET, a breakdown voltage structure such as a guard ring is provided to keep its breakdown voltage stable, however, in the MOSFET of the trench multi RESURF structure shown in FIG. 12, the guard ring itself may cause the charge unbalance, therefore, the conventional breakdown voltage structure for the terminating portion can never be employed. It is conceivable that, in order to eliminate influences of the redundant N layer and P layer in the terminating portion, a trench width between the N and P layers (a lateral distance of the insulator separating therebetween) is enlarged to thereby maintain the breakdown voltage at the insulator in the trench. However, the width of the insulator is required not less than 6 im to stably form a device having the breakdown voltage of 600V, for example. There is yet no technique of completely burying an insulator in such a wide trench.